Dr. Preeti Chauhan is a Technical Program Manager (TPM) in the Data Center Quality and Reliability group at Google. Previously, Dr Chauhan was a Quality and Reliability TPM at Intel and led the Assembly and Test certification of Foveros 3D packaging technology and Server microprocessors. She is a senior member of IEEE and co-editor of the data column in the Computer magazine.

Shubhada Sahasrabudhe is a Principal Engineer at Intel Corporation. She received her Master’s Degree in Mechanical Engineering from University of Maryland, College park. Her current role in Intel is Data Center Fleet Quality Fleet. Over her 20+ years journey at Intel, Shubhada has led efforts with focus on developing Use Conditions and Physics based Reliability Models to enable Knowledge Based Qualification, Mechanics based Predictive Reliability Modeling, Advanced Statistical Models for Power-Performance-Reliability Optimization, Process-Design-Material based Q&R risk assessment strategies, new packaging material qualification and Product World Class Quality Modeling. Shubhada holds over 12 patents and has over 30 publications with several best paper awards. She received an esteemed “2021 Woman in Engineering Award” from American Society of Mechanical Engineers, Electronic & Photonic Packaging Division. She has a deep passion for mentoring engineers and actively coaches many mentees. She cherishes work-life balance by creating and teaching art at her fine art academy as well as spending time with her family.

Grace is a supplier quality engineer at Google. Previously Grace was in the research and development division of Micron, where she managed the development and qualification of dual inline memory modules.

Christina Peabody is the lead engineer for UPS batteries for Google’s data centers. She received her Ph.D. degree in Mechanical and Aerospace Engineering from Princeton University studying degradation mechanisms in Li-ion batteries. Prior to working at Google she developed fast charging algorithms for Li-ion batteries in consumer electronics with a Bay Area startup company. Christina has also taught graduate level courses in battery technologies and manufacturing as an adjunct faculty member for San Jose State University.

Ryuichi Teramoto is an expert in the Corporate Manufacturing Engineering Center, Toshiba Corporation, Yokohama, Japan. His research focuses on numerical simulation where he developed methods to improve semiconductor device yield using quality control data from the production line. Ryuchi received B.S. and M.S. degrees in Mechanical Engineering and Materials Science from Yokohama National University.

Dinesh Thanu is an Engineering Manager and Technologist for Pathfinding, Assembly and Packaging technologies at Intel. He joined Intel in 2011 after earning a PhD in Materials Science and Engineering from the University of Arizona. He represents Intel in conference leadership and participation in various student forums. As a passionate inventor in microelectronics packaging technologies, Dinesh holds more than 10 patent applications, including the best innovator award from Intel in 2017. Dinesh has written 5 book chapters and more than 25 publications on topics related to his area of expertise and has received a best paper award from Intel in 2013. His contributions during his Intel career have earned him numerous honors, including the Outstanding Technical Contributor award in 2017 from IEEE Phoenix EPS Chapter, nomination for Early Career Engineer award in 2019 from ASME Electronic and Photonic Packaging Division, Senior IEEE membership and editorial roles in several international journals.